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is43/46lr16800e 2m x 16bits x 4banks mobile ddr sdram description the is43/46lr16800e is 134,217,728 bits cmos mobile double data rate synchronous dram organized as 4 banks of 2,097,152 words x 16 bits. this product uses a double-data-rate architecture to achi eve high-speed operation. the da ta input/ output signals are t ransmitted on a 16-bit bus. the double data rate architecture is essentially a 2 n prefetch architecture with an interface designed to transfer two data words per clock cycle at the i/o pins. this product offers fully synchronous operations referenced to both rising and falling edg es of the clock. the data paths are internally pipelined and 2n-bits prefetched to achieve very high bandwidth. all input and output voltage levels are compatible with lvcmos compatible with lvcmos . features ? jedec standard 1.8v power supply. ? vdd = 1.8v, vddq = 1.8v ? four internal banks for concurrent operation ? mrs c y cle with address ke y p ro g rams ? 64ms refresh period (4k cycle) ? auto & self refresh ? concurrent auto precharge ? maximum clock fre q uenc y u p to 166mhz y yp g - cas latency 2, 3 (clock) - burst length (2, 4, 8, 16) - burst type (sequential & interleave) ? fully differential clock inputs (ck, /ck) ? all inputs except data & dm are sampled at the rising edge of the system clock ? data i/o transaction on both edges of data strobe ? bidirectional data strobe per byte of data (dqs) qyp ? maximum data rate up to 333mbps/pin ? special power saving supports. - pasr (partial array self refresh) - auto tcsr (temperature compensated self refresh) - deep power down mode - programmable driver strength control by full strength or 1/2, 1/4, 1/8 of full strength ? lvcmos compatible inputs/outputs bidirectional data strobe per byte of data (dqs) ? dm for write masking only ? edge aligned data & data strobe output ? center aligned data & data strobe input lvcmos compatible inputs/outputs ? 60-ball fbga package copyright ? 2010 integrated silicon solution, inc. all rights reserv ed. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, prod ucts or services described herein. customers are advised to obtain the latest vers ion of this device specificat ion before relying on any publish ed information and before placing orders for products. 1 1 rev. a | april 2010 www.issi.com - dram@issi.com integrated silicon solution, inc. does not recommend the use of any of its products in life support applications where the fail ure or malfunction of the product can reasonably be ex pected to cause failure of the life support system or to significantly affect it s safety or effectiveness. products are not authorized for use in such applicat ions unless integrated silicon solution, inc. receives writt en assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of integrated silicon soluti on, inc is ade quately protec ted under the circumstances
is43/46lr16800e figure1: 60ball fbga ball assignment a 1 2 3 4 5 6 7 8 9 vss dq15 vssq vddq dq0 vdd b c d vddq dq13 dq14 vssq dq11 dq12 vddq dq9 dq10 dq1 dq2 vssq dq3 dq4 vddq dq5 dq6 vssq e f vss udm nc nc ldm vdd vssq udqs dq8 dq7 ldqs vddq g h j cke ck /ck a9 a11 nc a6 a7 a8 /we /cas /ras /cs ba0 ba1 a10 a0 a1 k vss a4 a5 a2 a3 vdd [top view] 2 rev. a | april 2010 www.issi.com - dram@issi.com
is43/46lr16800e table2 : pin descriptions symbol type function descriptions symbol type function descriptions ck, /ck input system clock the system clock input. ck and /ck are differential clock inputs. all address and control input signals are registered on the crossing of the rising edge of ck and falling edge of /ck. input and output data is referenced to the crossing of ck and /ck. cke input clock enable cke is clock enable controls in put. cke high activates, and cke low deactivates internal clock signals, and device input buffers and output drivers. cke is synchronous for all functions tf selfrefreshexit hi hi hi d excep t f or self refresh exit , w hi c h i s ac hi eve d asynchronously. /cs input chip select /cs enables (registered low) and disables (registered high) the command decoder. all commands are masked when /cs is registered high. /cs provides for external bank selection on systems with multiple banks. /cs is considered part of the command code. ba0 and ba1 define to which bank an active, read, write, or precharge command is being applied. ba0 and ba1 also ba0, ba1 input bank address determine which mode register (standard mode register or extended mode register) is loaded during a load mode register command. a0~a11 input address row address : ra0~ra11 column address : ca0~ca8 auto precharge : a10 /ras, /cas, /we input row address strobe, column address strobe, wit e bl /ras, /cas and /we define the operation. refer function truth table for details. w r it e e na bl e ldm, udm input data input mask dm is an input mask signal for write data. input data is masked when dm is sample d high along with that input data during a write access. dm is sampled on both edges of dqs. although dm balls are input-only. dq0 ~ dq15 in/output data input/output data input/output pin . dq0 dq15 in/output data input/output data input/output pin . ldqs, udqs in/output data input/output strobe output with read data, input with write data. dqs is edge- aligned with read data, centered in write data. data strobe is used to capture data. vdd supply power supply power supply vss supply ground ground vss supply ground ground vddq supply dq power supply power supply for dq vssq supply dq ground ground for dq nc nc no connection no connection. 3 rev. a | april 2010 www.issi.com - dram@issi.com
is43/46lr16800e figure2 : functional block diagram extended mode register self refresh logic & timer internal row write data register 2-bit prefetch unit input bu f ds x16 x32 pasr internal row counter row pre decoder state m row decod e row d e ro w 2mx16 bank 1 2mx16 bank 0 2mx16 bank 2 2mx16 bank 3 f fer & logic x32 row active /cs cke ck /ck column pre decoder m achine e rs e coders w decoders row decoders memory cell array column decoders sense amp&i/o gate output buffer & logic dq0 . . . . . . . dq15 | | 16 | | | | 32 | | refresh column active ldm/udm /we /cas /ras column add counter address register burst udqs,ldqs bank select a0 a1 register mode register data out control counter address buffers data strobe transmitter data strobe receiver ds burst length cas latency --------- a1 a11 ba0 ba1 4 rev. a | april 2010 www.issi.com - dram@issi.com
is43/46lr16800e figure3 : simplified state diagram power on precharge a ll b k deep power down s elf r efresh dpds power applied dpdsx a ll b an k s mrs emrs idle all banks precharged r efresh auto refresh mrs refa refsx refs ckel active power down row active burst stop precharge power down act ckeh ckel ckeh write read write read bst write a write read read a read write a read a precharge preall write a read a pre pre pre pre automatic se q uence q act = active bst = burst ckel = enter power- down ckeh = exit power-down preall= precharge all banks refa = auto refresh refs = enter self refresh refsx = exit self refresh 5 rev. a | april 2010 www.issi.com - dram@issi.com dpds = enter deep power-down dpdsx = exit deep power- down emrs = ext. mode reg. set mrs = mode register set pre = precharge read = read w/o auto prechar g e read a = read with auto precharge write = write w/o auto precharge write a = write with auto precharge
is43/46lr16800e a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 figure4 : mode register set (mrs) definition ba0 ba1 address bus 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000 cas latency bt burst length mode register (mx) m3 burst type 0sequential 1interleave m6 m5 m4 cas latency 000 reserved 001 reserved 010 2 011 3 100 reserved 101 reserved 1 1 0 reserved m2 m1 m0 burst length m3 = 0 m3 = 1 0 0 0 reserved reserved 001 2 2 010 4 4 011 8 8 1 0 0 16 16 1 0 1 reserved reserved burst type accesses within a given burst may be programmed to be either seque ntial or interleaved; this is referred to as the burst type and is selected via bit m3. the ordering of accesses within a burst is determined by the burst length, the burst type and the starting column add ess as sho n in table 3 1 1 0 reserved 111 reserved 1 0 1 reserved reserved 1 1 0 reserved reserved 1 1 1 reserved reserved note: m13(ba1) and m12(ba0) must be set to ?0? to select mode register (vs. the extended mode register) add r ess , as sho w n in table 3 . 6 rev. a | april 2010 www.issi.com - dram@issi.com
is43/46lr16800e table3 : burst definition burst length starting column address order of access within a burst a3 a2 a1 a0 sequential mode interleave mode a3 a2 a1 a0 sequential mode interleave mode 2 xxx0 0-1 0-1 xxx1 1-0 1-0 4 x x 0 0 0-1-2-3 0-1-2-3 x x 0 1 1-2-3-0 1-0-3-2 x x 1 0 2-3-0-1 2-3-0-1 xx11 3-0-1-2 3-2-1-0 0 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 x 0 0 0 0 - 1 - 2 - 3 - 4 - 5 - 6 - 7 0 - 1 - 2 - 3 - 4 - 5 - 6 - 7 x001 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 x010 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 x011 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 x100 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 x101 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 x 1 1 0 6 - 7 - 0 - 1 - 2 - 3 - 4 - 5 6 - 7 - 4 - 5 - 2 - 3 - 0 - 1 x 1 1 0 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1 x111 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 000 0 0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15 0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15 000 1 1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-0 1-0-3-2-5-4-7-6-9-8-11-10-13-12-15-14 001 0 2-3-4-5-6-7-8-9-10-11-12-13-14-15-0-1 2-3-0-1-6-7-4-5-10-11-8-9-14-15-12-13 001 1 3-4-5-6-7-8-9-10-11-12-13-14-15-0-1-2 3-2-1-0-7-6-5-4-11-10-9-8-15-14-13-12 010 0 4-5-6-7-8-9-10-11-12-13-14-15-0-1-2-3 4-5-6-7-0-1-2-3-12-13-14-15-8-9-10-11 16 010 1 5-6-7-8-9-10-11-12-13-14-15-0-1-2-3-4 5-4-7-6-1-0-3-2-13-12-15-14-9-8-11-10 011 0 6-7-8-9-10-11-12-13-14-15-0-1-2-3-4-5 6-7-4-5-2-3-0-1-14-15-12-13-10-11-8-9 011 1 7-8-9-10-11-12-13-14-15-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0-15-14-13-12-11-10-9-8 100 0 8-9-10-11-12-13-14-15-0-1-2-3-4-5-6-7 8-9-10-11-12-13-14-15-0-1-2-3-4-5-6-7 100 1 9-10-11-12-13-14-15-0-1-2-3-4-5-6-7-8 9-8-11-10-13-12-15-14-1-0-3-2-5-4-7-6 101 0 10-11-12-13-14-15-0-1-2-3-4-5-6-7-8-9 10-11-8-9-14-15-12-13-2-3-0-1-6-7-4-5 101 1 11-12-13-14-15-0-1-2-3-4-5-6-7-8-9-10 11-10-9-8-15-14-13-12-3-2-1-0-7-6-5-4 110 0 12-13-14-15-0-1-2-3-4-5-6-7-8-9-10-11 12-13-14-15-8-9-10-11-4-5-6-7-0-1-2-3 110 1 13-14-15-0-1-2-3-4-5-6-7-8-9-10-11-12 13-12-15-14-9-8-11-10-5-4-7-6-1-0-3-2 111 0 14-15-0-1-2-3-4-5-6-7-8-9-10-11-12-13 14-15-12-13-10-11-8-9-6-7-4-5-2-3-0-1 111 1 15-0-1-2-3-4-5-6-7-8-9-10-11-12-13-14 15-14-13-12-11-10-9-8-7-6-5-4-3-2-1-0 note : 1. for a burs t len g th o f two, a1-a8 selec t the block o f two burs t ; a0 selects the startin g column within the block. 2. for a burst length of four, a2-a8 select the block of four b urst; a0-a1 select the starting column within the block. 3. for a burst length of eight, a3-a8 select the block of eight burst; a0-a2 select the starting column within the block. 4. for a burst length of sixteen, a4-a8 select the block of eight burst; a0-a3 select the starting column within the block. 5. whenever a boundary of the block is reached within a given se quence above, the following access wraps within the block. 7 rev. a | april 2010 www.issi.com - dram@issi.com
is43/46lr16800e figure5 : extended mode set (emrs) register a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 ba0 ba1 address bus extended mode register (ex) 131211109876543210 1000000 ds 00 pasr e2 e1 e0 self refresh coverage 000four banks 001two bank (ba1=0) 0 1 0 one bank (ba1=ba0=0) 0 1 1 reserved 1 0 0 reserved e6 e5 driver strength 0 0 full strength 0 1 1/2 strength 1 0 1/4 strength 1 1 1/8 strength 1 0 0 reserved 101 one eighth of total bank (ba1 = ba0 = row address msb=0) 110 one sixteenth of total bank (ba1 = ba0 = row address 2 msbs=0) 1 1 1 reserved note: e13(ba1) and e12(ba0) must be set to ?1,0? to select extend mode re g ister (vs. the base mode re g ister) 8 rev. a | april 2010 www.issi.com - dram@issi.com
is43/46lr16800e t he 128mb mobile ddr sdram is a hi g h-s p eed cmos , d y namic random-access memor y containin g 134 , 271 , 728-bits. i t is internall y functional description g p , y y g , , y configured as a quad-bank dram. the 128mb mobile ddr sdram uses a do uble data rate architecture to achieve high speed operation. thedoubledataratearchitectureisessentiallya2n-prefetcharchitec ture, with an interface designed to transfer two data words per clock cycle at the i/o balls, single read or write access for the 128mb mobile ddr sdram consists of a single 2n-bit wide, one-clock-cycle data transfer at the internal dram core and two corresponding n-bit w ide, one-half-clock-cycle data transfers at the i/o balls. read and write accesses to the mobile ddr sdram are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration of an active command, which is then followed by a read or write command. the address bits registered coincident with the active command are used to select the bank and row to be accessed (ba0, ba1 select the bank; a0?a11 select the row). the address bits registered coincident with the read or write command are used to select the starting column location for the burst access. it should be noted that the dll signal that is typically used on standard ddr devices is not necessary on the mobile ddr sdram. it has been omitted to save power. prior to normal operation, the mobile ddr sdram must be powered up and i nitialized. the following sections provide detailed information covering device initialization, register definition, command descriptions and device operation. power up and initialization mobile ddr sdram must be powered up and initialized in a predefined manner. power must be applied to vdd and vddq (simultaneously). after power up, an initial pause of 200 usec is required. and a precharge all command will be issued to the mobile ddr. then, 2 or more auto refresh cycles will be provided. after the auto refresh cycles are completed, a mode register set(mrs) command will be issued to program the specific mode of operation (cas latency, burst length, e tc.) and a extended mode register set(emrs) command will be issued to partial array self refresh(pasr). the following these cycles, the mobile ddr sdram is ready for normal operation. to ensure device functionalit y, there is a p redefined se q uence tha t mus t occur a t device p ower u p or i f there is an y interru p tion o f device p ower. y, p q p p y p p to properly initialize the mobile ddr sdram, this sequence must be followed: 1. to prevent device latch-up, it is recommen ded the core power (vdd) and i/o power (vddq) be from the same power source and brought up simultaneously. if separate power sources are used, vdd must lead vddq. 2. once power supply voltages are stable and the cke has been driven high, it is safe to apply the clock. 3. once the clock is stable, a 200 s (minimum) delay is required by the mobile ddr sdram prior to applying an executable command. during this time, nop or deselect commands must be issued on the command bus. 4. issue a precharge all command. 5. issue nop or deselect commands for at least trp time. 6. issue an auto refresh command followed by nop or deselect commands for at least trfc time. issue a second auto refresh commandfollowedbynopordeselectcommandsforatleasttrfcti me. as part of the individualization sequence, two auto refresh commands must be issued. typically, both of these co mmands are issued at this st age as described above. 7. using the load mode register command, load the standard mode register as desired. 8. issue nop or deselect commands for at least tmrd time. 9. usin g the load mode register command, load the extended mode re g ister to the desired operatin g modes. note tha t the order in which the standard and extended mode reg isters are programmed is not critical. 10. issue nop or deselect commands for at least tmrd time. 11. the mobile ddr sdram has been properly initialized and is ready to receive any valid command. 9 rev. a | april 2010 www.issi.com - dram@issi.com
is43/46lr16800e figure6 : power up sequence clk /clk t0 t1 ta0 tcl tb0 tc0 td0 te0 tf0 cos vddq vdd act all mrs mrs aref aref pcg nop nop 2 nop 3 cke command 1 a0~a9, a11 lv c m os high level a 10 ra code code tis tih ra code code tis tih tis tih ba ba0=l, ba1=h ba0=l, ba1=l all banks dm a 10 ba0, ba1 dqs, dq high-z tis ra code code tis tih tih tck t = 200 s trp 4 trfc 4 trfc 4 tmrd 4 tmrd 4 load standard mode register load extended mode register power-up: vdd and c lk stable don ? t care notes: 1. pcg = precharge command, mrs = load mode register command, aref = autorefresh command, act = active command, ra = row address, ba = bank address. 2. nop or deselect commands are required for at least 200 s. 3. other valid commands are possible. 4. nops or deselects are required during this time. 10 rev. a | april 2010 www.issi.com - dram@issi.com
is43/46lr16800e mode register the mode register is used to define the specific mode of operation of the mobile ddr sdram. this definition includes the selection of a burs t len g th, a burs t type, a cas latency. t he mode re g ister is pro g rammed via the load mode register command and will retain the stored information until programmed again, the device goes into deep power-down mode, or the device loses power. mode register bits a0-a2 specify the burst length, a3 specifies the typ e of burst (sequential or interleaved), a4-a6 specify the cas latency, and a7-a11 should be set to zero. ba0 and ba1 must be zero to access the mode register. the mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent operation. violating either of these requir ements will result in unspecified operation. burst length read and write accesses to the mobile ddr sdram are burst oriented, with the burst length being programmable, as shown in figure (mode register set definition). the burst length determines the m aximum number of column locations that can be accessed for a given read or write command. burst lengths of 2, 4,8 or 16 are availab le for both the sequential and the interleaved burst types. reserved states should not be used, as unknown operation or incompatibility with future versions may result. when a read or write command is issued, a block of columns equal to the burst length is effectively selected . all accesses for that burst take place within this command is issued, a block of columns equal to the burst length is effectively selected . all accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. the block is uniquely selected by a1-a8 when the burst length is set to two; by a2-a8 when the burst length is set to four; by a3-a8 when the burst length is set to eight; and by a4-a8 when the burst length is set to sixteen. the remaining (least significant) address bit(s) is (are) used to select the starting location within the block. the programmed burst length app lies to both read and write bursts. cas latency the cas latency is the delay, in clock cycles, between the registrat ion of a read command and the availability of the first bit of output data. the latency can be set to 2, 3 clocks, as shown in figure (standard mode register definition). for cl = 3, if the read command is registered at clock edge n, then the data will be available at (n + 2 clocks + tac). for cl = 2, if the read command is registered at clock edge n, then th e data will be available at (n + 1 clock + tac). figure7 : cas latency (bl=4) / c k t 0 t 1 t2 t3 t1n t2n t3n t4 t4n l / c k ck command read nop nop nop nop tac cl=2 trpre 1tck trpst l l tac cl=3 trpre 2tck trpst dqs dq d out n+1 d out n d out n+2 d out n+3 11 rev. a | april 2010 www.issi.com - dram@issi.com dqs dq d out n+1 d out n d out n+2 d out n+ 3 don ?t care
is43/46lr16800e extended mode register the extended mode register controls the functions beyond those controlled by the mode register. these additional functions are special features of the mobile ddr sdram. they include partial array self refresh (pasr) and driver strength (ds). t he extended mode re g ister is pro g rammed via the mode re g ister se t command (ba0=0, ba1=1) and retains the stored information until programmed again, the device goes into deep power-down mode, or the device loses power. theextendedmoderegistermustbeprogrammedwitha7througha11setto?0?.theextendedmoderegistermustbeloadedwhenall banks are idle and no bursts are in progress, and the controller must w ait the specified time before initiating any subsequent operation. violating either of these requirements results in unspecified operation. partial a rra y self refresh y for further power savings during self refresh, the pasr feature allows the controller to select the amount of memory that will be refreshed during self refresh. the refresh options are as follows: ? full array: banks 0, 1, 2, and 3 ? half array: banks 0 and 1 ? quarter array: bank 0 ? one eight array: half of bank 0 ? one sixteen array: quarter of bank 0 write and read commands can still occur during standard operation, b ut only the selected banks will be refreshed during self refresh. dt i bk th t di bl d ill b lt d a t a i n b an k s th a t are di sa bl e d w ill b e l os t . output driver strength because the mobile ddr sdram is designed for use in smaller systems that are mostly point to point, an option to control the drive strength of the output buffers is available. drive strength should be selected based on the expected loading of the memory bus. bits a5 and a6 of the extended mode register can be used to select the driver strength of the dq outputs. there are four allowable settings for the output drivers. temperature compensated self refresh temperature compensated self refresh in the mobile ddr sdram, a temperature sensor is implemented for automatic control of the self refresh oscillator on the device. temperature compensated self refresh allows the controller to progr am the refresh interval during self refresh mode, according to the case temperature of the mobile sdram device. this allows great power savings during self refresh during most operating temperature ranges. only during extreme temperatures would the controller have to select a tcsr level that will guarantee data during self refresh. every cell in the dram requires refreshing due to the capacitor losin g its charge over time. the refresh rate is dependent on temperature. at higher temperatures a capacitor loses charge quicker than at lo wer temperatures, requiring the cells to be refreshed more often. historically, during self refresh, the refresh rate has been set to accommodate the worst case, or highest temperature range expected. thus, during ambient temperatures, the power consumed during r efresh was unnecessarily high, because the refresh rate was set to accommodate the higher temperatures. this temperature compensated refresh rate will save power when the dram is operating at normal temperatures. 12 rev. a | april 2010 www.issi.com - dram@issi.com
is43/46lr16800e commands the following commands truth table and dm op eration truth table provide quick reference of available commands. this is followe dby a written description of each command. deselect the deselect function (/cs high) prevents new commands from being executed by the mobile ddr sdram. the mobile ddr sdram is effectively deselected. operations al ready in progress are not affected. no operation (nop) the no operation (nop) command is used to instruct the selected ddr sdram to perform a nop (/cs = low, /ras = /cas = /we = high). this prevents unwanted commands from being registered during idle or wait states. operations already in progress are not a ffected. active the active command is used to open (or ac tivate) a row in a particular bank for a su bsequent access. the value on the ba0, ba1 i nputs selects the bank, and the address provided on inputs a0?a11 selects the row. this row remains active (or open) for accesses until a precharge command is issued to that bank. a precharge command must be issued before opening a different row in the same bank. read t he read command is used to initiate a burst read access to an active row. t he value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0?a8 selects the starting column loca tion. the value on input a10 determines whether or not auto prech arge is used. if auto precharge is selected, the ro w being accessed will be precharged at the end of the read burst; if auto precharge is not selected, the row will remain open for subsequent accesses. write the write command is used to initiate a burst write access to an active row. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0-a8 selects the starting column loca tion. the value on input a10 determines whether or not auto prech arge is used if auto precharge is selected the row being accessed will be precharged at the end of the write burst; if auto precharge is not used . if auto precharge is selected , the row being accessed will be precharged at the end of the write burst; if auto precharge is not selected, the row will remain open for subs equent accesses. input data appearing on the dqs is written to the memory array subje ct to the dm input logic level appearing coincident with the data. if a given dm signal is registered low, the corresponding data will be w ritten to memory; if the dm signal is registered high, the corresponding da ta inputs will be ignored, and a write will not be executed to that byte/column location. precharge the precharge command is used to deactivate the open row in a particular bank or the op en row in all banks. the bank(s) will be available for a subse q uent row access a s p ecified time ( trp ) after the p rechar g e command is issued. exce p t in the case of concurren t auto p rechar g e , q p()pg p pg, where a read or write command to a different bank is allowed as long as it does not interrupt the data transfer in the current b ank and does not violate any other timing parameters. input a10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs ba0, ba1select the bank. otherwise ba0, ba1 are treated as ?don?t care.? once a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. a precha rge command will be treated as a nop if there is no open row in that bank (idle state), or if the prev iously open row is already in t he process of precharging. 13 rev. a | april 2010 www.issi.com - dram@issi.com
is43/46lr16800e auto precharge auto precharge is a feature which performs the same individual-b ank precharge function described above, but without requiring a n explicit command this is accomplished by using a10 to enable auto precharge in conjunction with a specific read or write command a command . this is accomplished by using a10 to enable auto precharge in conjunction with a specific read or write command . a precharge of the bank/row that is addressed with the read or write command is automatically performed upon completion of the re ad or write burst. auto precharge is nonpersistent in that it is either enabled or disabled for each individual read or write comman d. this device supports concurrent auto precharge if the command to the other bank does not interrupt the data transfer to the current bank. auto precharge ensures that the precharge is initiated at the earliest valid stage within a burst. this ?earliest valid stage? is de termined as if an explicit precharge command was issued at the earliest possible time, without violating tras (min). the user must not issue anot her command to the same bank until the precharge time (trp) is completed. b urst t erminate b urst t erminate the burst terminate command is used to truncate read bursts (with auto precharge disabled). the most recently registered read command prior to the burst terminate command will be truncated. the open page which the read burst was terminated from remains open. auto refresh auto refresh is used during no rmal operation of the mobile ddr sdram and is analogous to /cas-before-/ras (cbr) refresh in fpm/edo drams. this command is nonpersistent, so it must be issu ed each time a refresh is required. the addressing is generate dby the internal refresh controller this makes the address bits a ?don?t care? during an auto refresh command the 128mb mobile dd rs dram internal refresh controller . this makes the address bits a ?don?t care? during an auto refresh command . the 128mb mobile dd r s dram requires auto refresh cycles at an average interval of 15.6 s (maximum). to allow for improved efficiency in sche duling and switching between tasks, some flexibility in the absolute refresh interval is provided. although not a jedec requirement, to provide for future functionality features, cke must be active (high) during the auto refre sh period. the auto refresh period begins wh en the auto refresh command is registered and ends trfc later. self refresh the self refresh command can be used to retain data in the mobile ddr sdram, even if the rest of the system is powered down. wh en hlffhdh bl d h llk h d d lk in t h e se lf re f res h mo d e, t h e mo b i l e ddr sdram retains d ata wit h out externa l c l oc k in g . t h e self refresh comman d is initiate d l i k e an auto refresh command except cke is disabled (low). all command and address input signals except cke are ?don?t care? during se lf refresh. during self refresh, the device is refreshed as identified in the external mode register (see pasr setting). for a the full arr ay refresh, all four banks are refreshed simultaneously with the refresh frequenc y set by an internal self refresh oscillator. this oscillator changes due to the temperature sensors input. as the case temperature of the mobile ddr sdram increases, the oscillation frequency will chang eto accommodate the change of temperature. this happens because the dram capacitors lose charge faster at higher temperatures. to ensure efficient power dissipation during self refresh, the oscillator will change to refresh at the slowest rate possible to maintain the devices data. the procedure for exiting self refresh r equires a sequence of commands first c lock must be stable prior to cke going back high once the procedure for exiting self refresh requires a sequence of commands . first , c lock must be stable prior to cke going back high . once cke is high, the mobile ddr sdram must have nop commands issued for txsr is required for the completion of any internal refresh in progress. deep power-down deep power down is an operating mode to achieve maximum power reduction by eliminating the power of the whole memory array of th e devices. data will not be retained once the device enters deep power down mode. this mode is entered by having all banks idle then /cs and /we he ld low with /ras and /cas held high at the rising edge of the clock, while cke is low. this mode is exited by assertin g cke hi g h. 14 rev. a | april 2010 www.issi.com - dram@issi.com
is43/46lr16800e function /cs /ras /cas /we ba a10/ap addr note table4: command truth table deselect (nop) h x x x x x x 2 no operation (nop) l h h h x x x 2 active (select bank and activate row) l l h h v row row read (select bank and column and start read burst) l h l h v l col read with ap (read burst with auto recharge) l h l h v h col 3 write (s l t b k d l d t t it b t) l h l l v l cl write (s e l ec t b an k an d co l umn an d s t ar t wr it e b urs t) l h l l v l c o l write with ap (write burst with auto recharge) l h l l v h col 3 burst terminate or enter deep power down l h h l x x x 4,5 precharge (deactivate row in selected bank) l l h l v l x 6 precharge all (deactivate ro ws in all banks) l l h l x h x 6 auto refresh or enter self refresh l l l h x x x 7,8,9 auto refresh or enter self refresh l l l h x x x 7,8,9 mode register set l l l l v op_code 10 function dm dq note write enable l valid 11 wit i hibit h x 11 table5 : dm truth table note: 1. all states and sequences not shown are illegal or reserved. 2. deslect and nop are functionally interchangeable. 3. autoprecharge is non-persistent. a10 high enables autoprecharge, wh ile a10 low disables autoprecharge 4. burst terminate applies to only read bursts with autoprecharge disabled. w r it e i n hibit h x 11 t his command is undefined and should no t be used for read with autoprechar g e enabled, and for write bursts. 5. this command is burst terminate if cke is high and deep power down entry if cke is low. 6. if a10 is low, bank address determines which bank is to be precharged. if a10 is high, all banks are precharged and ba0-ba1 a re don?t care. 7. this command is auto refresh if cke is high, and self refresh if cke is low. 8. all address inputs and i/o are ''don't care'' except for ck e. internal refresh counters control bank and row addressing. 9. all banks must be precharged before issuing an auto-refresh or self refresh command. 10. ba0 and ba1 value select between mrs and emrs. 11. used to mask write data, provided coincident with the corresponding data. 12. cke is high for all commands shown ex cept self refresh and deep power-down. 15 rev. a | april 2010 www.issi.com - dram@issi.com
is43/46lr16800e note action n command n current state cken cken 1 table6 : cke truth table 5,7,10 exit self refresh nop or deselect self refresh h l 5,6,9 exit power down nop or deselect power down h l maintain deep power down x deep power down l l maintain self refresh x self refresh l l maintain power down x power down l l note action n command n current state cken cken - 1 en te r d eep p o w e r b u r s t terminate all b a nk s i d l e l h self refresh entry auto refresh all banks idle l h 5 active power down entry nop or deselect bank(s) active l h 5 precharge power down entry nop or deselect all banks idle l h 5,8 exit deep power down nop or deselect deep power down h l note: 1. cken is the logic stat e of cke at clock edge n ; cke n -1 was the state of cke at the previous clock edge. 2. current state is the state of mobile ddr immediately prior to clock edge n . 3 command i th d i t d t l k d d action i th lt f command see the other truth tables h h te eep o e down us asde 3 . command n i s th e comman d re gi s t ere d a t c l oc k e dg e n, an d action n i s th e resu lt o f command n . 4. all states and sequences not shown are illegal or reserved. 5. deselect and nop are f unctionally interchangeable. 6. power down exit time (txp) should elapse before a command other than nop or deselect is issued. 7. self refresh exit time (txsr) should elapse befo re a command other than nop or deselect is issued. 8. the deep power-down exit procedure must be followed as discussed in the deep power-down section of the functional description . 9. the clock must toggle at least one time during the txp period. 10. the clock must toggle at least once during the txsr time. 16 rev. a | april 2010 www.issi.com - dram@issi.com
is43/46lr16800e table7 : current state bank n truth table (command to bank n ) current state command action note /cs/ras/cas/we description any h x x x deselect(nop) continue previous operation l h h h nop continue previous operation l l h h active select and activate row ll lha u t o refresh a u t o refresh 1 0 idle uo uo 0 ll ll mode register set mode register set 10 l l h h precharge no action if bank is idle row active l h l h read select column & start read burst l h l l write select column & start write burst l l h l precharge deactivate row in bank (or banks) 4 read (without auto recharge) l h l h read truncate read & start new read burst 5,6 l h l l write truncate read & start new write burst 5,6,13 l l h l precharge truncate read, start precharge l h h l burst terminate burst terminate 11 write (without auto l h l h read truncate write & start new read burst 5,6,12 l h l l write truncate write & start new write burst 56 note: 1. the table applies when both cken-1 and cken are high, and after txsr or txp has been met if the previous state was self refr esh or power down. 2. deselect and nop are f unctionally interchangeable. 3all tt d t h ill l d (without auto precharge) l h l l write truncate write & start new write burst 5 , 6 l l h l precharge truncate write, start precharge 12 3 . all s t a t es an d sequences no t s h own are ill e g a l or reserve d . 4. this command may or may not be bank specific. if all banks are being precharged, they must be in a valid state for prechargi ng. 5. a command other than nop should not be issued to the same bank while a read or write burst with auto precharge is enabled. 6. the new read or write command could be auto precharge enabled or auto precharge disabled. 7. current state definitions: idle: the bank has been prec harged, and trp has been met. row active: a row in the bank has been activated, and trcd has been met. no data bursts/accesses and no re gister accesses are in progress. read: a read burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. write: a write burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. 8. the following states must not be interrup ted by a command issued to the same bank. deselect or nop commands or allowable commands to the other ba nk should be issued on any clock edge occurring during these states. allowable commands to the other bank are determined by its current state and truth table3 , and according to truth table 4. ? precharging: starts with the registration of a precharge command and ends when trp is met. once trp is met, the bank will be in the idle state. ? row activating: starts with registration of an active command and ends when trcd is met. 17 rev. a | april 2010 www.issi.com - dram@issi.com once trcd is met, the bank will be in the ''row active'' state. ? read with ap enabled: starts with the registration of the read command with auto precharge enabled and ends when trp has been met. once trp has been met, the bank will be in the idle state. ? write with ap enabled: starts with registration of a write command with auto precharge enab led and ends when trp has been met. once trp is met, the bank will be in the idle state.
is43/46lr16800e 9. the following states must not be interrupted by any execut able command; deselect or nop commands must be applied to each positive clock edge during these states positive clock edge during these states . ? refreshing: starts with registration of an auto refresh command and ends when trfc is met. once trfc is met, the mobile ddr will be in an ''all banks idle'' state. ? accessing mode register: starts with registration of a mode register set command and ends when tmrd has been met. once tmrd is met, the mobile ddr will be in an ''all banks idle'' state. ? precharging all: starts with the registration of a precharge all command and ends when trp is met. once trp is met, the bank will be in the idle state. 10. not bank-specific; requires that all banks are idle and no bursts are in progress. 11. not bank-specific. burst terminate affects the most recent read burst, re g ardless of bank. 12. requires appropriate dm masking. 13. a write command may be applied after the completion of the read burst; otherwise, a burst terminate must be used to end the read prior to asserting a write command. 18 rev. a | april 2010 www.issi.com - dram@issi.com
is43/46lr16800e table8 : current state bank n truth table (command to bank m ) current state command action note /cs /ras /cas /we description any h x x x deselect(nop) continue previous operation l h h h nop continue previous operation idle x x x x any any command allowed to bank m l l h h active activ a te r o w row activating, active, or precharging ao lhlhread start read burst 8 l h l l write start write burst 8 l l h l precharge precharge read with auto precha rge disabled l l h h active activate row lhlhread state read burst 8 l h l l write start write burst 810 rge disabled l h l l write start write burst 8 , 10 l l h l precharge precharge write with auto precharge disabled l l h h active activate row lhlhread start read burst 8,9 l h l l write start write burst 8 l l h l precharge precharge read with auto precharge l l h h active activate row lhlhread start read burst 5,8 l h l l write start write burst 5,8,10 l l h l precharge precharge write with auto l l h h active activate row lhlhread start read burst 5,8 precharge l h l l write start write burst 5,8 l l h l precharge precharge 19 rev. a | april 2010 www.issi.com - dram@issi.com
is43/46lr16800e note: 1 the table applies when both cke n 1andcke n are high and after txsr or txp has been met if the previous state was self refresh or 1 . the table applies when both cke n - 1 and cke n are high , and after txsr or txp has been met if the previous state was self refresh or power down. 2. deselect and nop are f unctionally interchangeable. 3. all states and sequences not shown are illegal or reserved. 4. current state definitions: idle: the bank has been prec harged, and trp has been met. row active: a row in the bank has been activated, and trcd has be en met. no data bursts/accesses and no register accesses are in progress. read: a read burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. write: a write burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. 5. read with ap enabled and writ e with ap enabled: the read with autoprecharge enabled or write with au toprecharge enabled state s can be broken into two parts: the access period and the precharge period. for read with ap, the precharge period is defined as i f the same burst was executed with auto precharge disabled and then followed with the earliest possible precharge command that still accesses all the data in the burst. for write with auto precharge, the precharg e period begins when twr ends, with twr measured as if auto precharge was disabled. the access period starts with registration of the command and ends where the precharge period (or trp) begins. during the precharge period, of the read with autoprecharge enabled or write with autoprecharge enabled states, active, precharge, read, and write commands to the other bank may be applied; during the access period, only active and precharge commands to the other banks may be applied. in either case, all other related limitations apply (e.g. contention between read data and write data must be avoided). 6. auto refresh, self refr esh, and mode register set commands may on ly be issued when all bank are idle. 7. a burst terminate command cann ot be issued to another bank; it applies to the bank represented by the current state only. 8. reads or writes listed in the command column include reads and writes with auto precharge enabled and reads and writes with auto precharge disabled. 9. requires appropriate dm masking. 10. a write command may be applied after the completion of data output, otherwise a burst terminate command must be issued to end the read prior to asserting a write command. 20 rev. a | april 2010 www.issi.com - dram@issi.com
is43/46lr16800e table9 : absolute maximum rating parameter symbol rating unit ambient temperature (automotive) t a -40 ~ 85 c ambient temperature (industrial) -40 ~ 85 ambient temperature (commercial) 0 ~ 70 storage temperature t stg -55 ~ 150 c voltage on any pin relative to vss v in , v out -0.3 ~ 2.7 v v o l tage o n vdd r e l at iv e to v ss vdd , vdd q - 0 . 3 ~ 2.7 v voltage on vdd relative to vss vdd, vddq 0.3 2.7 v short circuit output current i os 50 ma power dissipation p d 0.7 w note : stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any ot her conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. table10 : dc operating condition (voltage referenced to vss=0v, t a = 0 ~ 70 c for commercial, or t a = -40 ~ 85 c for industrial or automotive) parameter symbol min typ max unit note power supply voltage vdd 1.7 1.8 1.95 v 1 power supply voltage vddq 1.7 1.8 1.95 v 1,2 input high voltage v ih (dc) 0.7 x vddq vddq + 0.3 v input low voltage v il (dc) -0.3 0.3 x vddq v output high voltage v oh (dc) 0.9 x vddq - v i oh =- 0.1ma output low voltage v ol (dc) - 0.1 x vddq v i ol =0.1m a note : 1. all voltages are referenced to vss = 0v 2. vdd and vddq must track each other, and vddq must not exceed the level of vdd input leaka g e curren t i li -2 2 ua output leakage current i lo -5 5 ua table11 : ac operating condition note : parameter symbol min max unit note input high voltage, all inputs v ih (ac) 0.8 x vddq vddq + 0.3 v input low voltage, all inputs v il (ac) -0.3 0.2 x vddq v input crossing point voltage, ck and /ck inputs v ix 0.4 x vddq 0.6 x vddq v 1 21 rev. a | april 2010 www.issi.com - dram@issi.com 1. the value of v ix is expected to equal 0.5*vddq of the transmitting device and must track variations in the dc level of the same.
is43/46lr16800e table12 : capacitance (t a =25 c, f=1mhz, vdd=1.8v) parameter pin symbol min max unit table13 : ac operating test condition input capacitance ck, /ck c i1 1.5 3.5 pf a0~a11, ba0~ba1, cke, /cs, /ras, /cas, /we c i2 1.5 3.0 pf ldm, udm c i3 24.5pf data & dqs input/output capacitance dq0~dq15, ldqs, udqs c io 24.5pf table13 : ac operating test condition (t a = 0 ~ 70 c for commercial, or t a = -40 ~ 85 c for industrial or automotive , vdd = 1.7v to 1.95v, vss=0v) parameter symbol value unit ac input high/low level voltage v ih / v il 0.8 x vddq / 0.2 x vddq v input timing measurement reference level voltage v trip 0.5 x vddq v input rise / fall time t r / t f 1 / 1 ns output timin g measurement reference level volta g ev outref 0.5 x vddq v output load capacitance for access time measurement c l 20 pf figure8 : output load circuit 13.9 k vddq 50 20pf output 20pf 50 table14 : ac overshoot/undershoot specification parameter specification maximum peak amplitude allowed for overshoot area 0.9v maximum peak amplitude allowed for undershoot area 0.9v dc output load circuit a c output load circuit maximum overshoot area above vdd/vddq 3v-ns maximum undershoot area below vss/vssq 3v-ns figure9 : ac overshoot/undershoot definition maximum amplitude vdd/vddq overshoot area 22 rev. a | april 2010 www.issi.com - dram@issi.com vdd/vddq vss/vssq voltage [v] maximum amplitude time [ns] undershoot area
is43/46lr16800e table15 : dc characteristic (dc operating conditions unless otherwise noted) paramete r s y mbol t est condition speed unit note y -60 -75 -10 operating one bank active- precharge current idd0 trc = trc(min), tck = tck(min), cke is high, /cs is high between valid commands, address inputs are switching, data bus inputs are stable 55 50 45 ma 1 precharge power-down standby current idd2p all banks idle, cke is low, /cs is high, tck = tck(min), address and control inputs are switching, data bus inputs are stable 0.3 ma precharge power-down standby idd2ps all banks idle, cke is low, /cs is high, ck = low, /ck = high a ddress and control inputs are 03 ma current with clock stop idd2ps /ck = high , a ddress and control inputs are switching, data bus inputs are stable 0 . 3 ma precharge non power-down standby current idd2n all banks idle, cke is high, /cs is high, tck = tck(min) , address and control inputs are switching, data bus inputs are stable 9.0 ma precharge non power-down standby current with clock stop idd2ns all banks idle, cke is high, /cs is high, ck = low, /ck = high, address and control inputs are switching, data bus inputs are stable 5.0 ma active power down standby one bank active , cke is low , / cs is high , tck = active power - down standby current idd3p , , /, tck(min), address and control inputs are switching, data bus inputs are stable 5.0 ma active power-down standby current with clock stop idd3ps one bank active, cke is low, /cs is high, ck = low, /ck = high, address and control inputs are switching, data bus inputs are stable 5.0 ma active non power-down standby current idd3n one bank active, cke is high, /cs is high, tck = tck(min), address and control inputs are switching, data bus inputs are stable 20 ma ati d o bk ti cke i high / cs i high ck a c ti ve non power- d own standby current with clock stop idd3ns o ne b an k ac ti ve, cke i s high , / cs i s high , ck = low, /ck = high, address and control inputs are switching, data bus inputs are stable 10 ma operating burst read current idd4r one bank active, bl=4, cl=3, tck = tck(min), continuous read bursts, iout=0ma, address inputs are switching, 50% data change each burst transfer 90 80 70 ma 1 operating burst write current idd4w one bank active, bl=4, tck=tck(min), continuous write bursts, address inputs are switching, 50% dt h hb tt f 90 80 70 ma 1 d a t a c h an g e eac h b urs t t rans f er auto refresh current idd5 trc=trfc(min), tck=tck(min), burst refresh, cke is high, address and control inputs are switching, data bus inputs are stable 90 ma 2 pasr tcsr 4 banks 85 c 350 45 c 300 85 c 210 1 bank 85 c 200 45 c 170 half bank 85 c 175 45 c 155 quarter 85 c 165 23 rev. a | april 2010 www.issi.com - dram@issi.com note : 1. measured with outputs open. 2. refresh period is 64ms. quarter bank 45 c 150 standby current in deep power down mode idd8 address and control inputs are stable, data bus inputs are stable 30 ua
is43/46lr16800e parameter symbol -60 -75 -10 unit note min max min max min max table16: ac characteristic (ac operation conditions unless otherwise noted) system clock cycle time cl=3 tck 67.510ns1 cl=2 10 10 10 ns 1 dq output access ti me from ck, /ck cl=3 tac 2.0 5.5 2.0 6.0 2.0 7.0 ns cl=2 2.0 8.0 2.0 8.0 2.0 8.0 clock high pulse width tch 0.45 0.55 0.45 0.55 0.45 0.55 tck clock low pulse width tcl 0. 45 0.55 0.45 0.55 0.45 0.55 tck c ke min. p u l se wi dt h ( hi g h / l o w pu l se wi dt h ) tc ke 1 1 1 tc k cke min. p ulse w idth (high / low pulse width) tcke 1 1 1 tck dq and dm input setup time tds 0.6 0.9 1.2 ns 2, 3, 4 dq and dm input hold time tdh 0.6 0.9 1.2 ns 2, 3, 4 dq and dm input pulse width tdipw 1.8 2.0 2.4 ns 5 address and control input setup time tis 1.1 1.3 1.5 ns 4, 6, 7 address and control input hold time tih 1.1 1.3 1.5 ns 4, 6, 7 address and control input pulse width tipw 2.7 3.0 3.4 ns 5 dq & dqs low impedance time from ck / ck tlz 10 10 10 ns 8 dq & dqs low - impedance time from ck , / ck tlz 1 . 0 1 . 0 1 . 0 ns 8 dq & dqs high-impedance time from ck, /ck thz 5.5 6 7 ns 8 dqs - dq skew tdqsq 0.5 0.6 0.7 ns 9 half clock period thp tch, tcl tch, tcl tch, tcl ns data hold skew fa ctor tqhs 0.65 0.75 1 ns dq / dqs output hold time from dqs tqh thp-tqhs thp-tqhs thp-tqhs ns write command to first dqs latching tr ansition tdqss 0.75 1.25 0.75 1.25 0.75 1.25 tck dqs i t hi h l width tdqsh 0 35 06 04 06 04 06 tck dqs i npu t high pu l se width tdqsh 0 . 35 0 . 6 0 . 4 0 . 6 0 . 4 0 . 6 tck dqs input low pulse width tdqsl 0.35 0.6 0.4 0.6 0.4 0.6 tck dqs falling edge to ck setup time tdss 0.2 0.2 0.2 tck dqs falling edge hold time from ck tdsh 0.2 0.2 0.2 tck access window of dqs from ck, /ck cl=3 tdqsck 2.0 5.5 2.0 6.0 2.0 7.0 ns cl=2 2.0 8.0 2.0 8.0 2.0 8.0 ns active to precharge command period tras 42 45 50 ns active to active command period trc 60 75 80 ns mode register set command cycle time tmrd 2 2 2 tck refresh period tref 64 64 64 ms average periodic refresh in terval trefi 15.6 15.6 15.6 us 10 auto refresh period trfc 70 70 70 ns active to read or write delay trcd 18 22.5 30 ns precharge command period trp 18 22.5 30 ns active bank a to active bank b delay trrd 12 15 15 ns write recovery time twr 12 15 15 ns auto precharge write recovery + precharge time tdal (twr/tck) + (trp/tck) internal write to read command delay twtr 111 tck dqs read preamble cl=3 trpre 0.9 1.1 0.9 1.1 0.9 1.1 tck 11 cl=2 0.5 1.1 0.5 1.1 0.5 1.1 tck 11 dqs read postamble trpst 0.4 0.6 0.4 0.6 0.4 0.6 tck 24 rev. a | april 2010 www.issi.com - dram@issi.com dqs write preamble twpre 0.25 0.25 0.25 tck dqs write preamble setup time twpres 000 ns12 dqs write postamble twpst 0.4 0.6 0.4 0.6 0.4 0.6 tck 13 exit power down to next valid command delay txp 111 tck self refresh exit to next valid command delay txsr 120 120 120 ns
is43/46lr16800e note : 1. the clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified fo rthe clock pin) during access or precharge states (read, write, including tdpl, and precharge commands). cke may be used to reduce the data rate. 2. 4. the transition time for dq, dm and dqs inputs is measured between vil(dc) to vih(ac) for rising input signals, and vih(dc ) to vil(ac) for falling input signals. 3. dqs, dm and dq input slew rate is specified to prevent double clocking of data and preserve setup and hold times. signal tran sitions through the dc region must be monotonic. 4 input slew rate 1.0v/ns (2.0v/ns if measured differentially) is assumed for this parameter. input setup/hold slew rate [v/ns] ? tds/ ? tis [ps] ? tdh/ ? tih [ps] 1.0 0 0 0.5 +150 +150 8. thz and tlz transitions occur in the same access time windows as valid data transitions. these parameters are not referred t o a specific voltage level, but specify when the device is no longer driving (hz), or begins driving (lz). 9. tdqsq consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for a ny given cycle. 1 0 a maximum of eight refresh commands can be posted to any given low power ddr sdram meaning that the maximum absolute ck,/ck setup/hold slew rate [v/ns] ? tds/ ? tis [ps] ? tdh/ ? tih [ps] 1.0 0 0 1 0 . a maximum of eight refresh commands can be posted to any given low - power ddr sdram , meaning that the maximum absolute interval between any refresh command an d the next refresh command is 8*trefi. 11. a low level on dqs may be maintained during high-z states (d qs drivers disabled) by adding a weak pull-down element in the s ystem. it is recommended to turn off the weak pull-down elem ent during read and write bursts (dqs drivers enabled). 12. the specific requirement is that dqs be valid (high, low, or some point on a valid transition) on or before this ck edge. a valid transition is defined as monotonic and meeting the input slew rate specifications of the device. when no writes were previously in progress on the bus, dqs will be transitioning from hi-z to logi c low. if a previous write was in progress, dqs could be high, l ow, or transitioning from high to low at this time, depending on tdqss. 1 3 th i li it f thi t i t d i li it th d i t ith t l f thi t b t t 1 3 . th e max i mum li m it f or thi s parame t er i s no t a d ev i ce li m it . th e d ev i ce opera t es w ith a g rea t er va l ue f or thi s parame t er, b u t sys t em performance (bus turnaround ) will degrade accordingly. 25 rev. a | april 2010 www.issi.com - dram@issi.com
is43/46lr16800e timing diagram bk/ ati ti b an k/ row a c ti va ti on the active command is used to activate a row in particular bank fo r a subsequent read or write access. the value of the ba0,ba1 inputs selects the bank, and the address provided on a0-a11(or the highest address bit) selects the row. before any read or write commands can be issued to a bank within the mobile ddr sdram, a row in that bank must be opened. this is accomplished via the active command, which selects both the bank and the row to be activated. the row remains active until a precharge (or read with auto precharge or write with auto precharge) command is issued to the bank. a precharge (or read with auto precharge or write with auto p recharge) command must be issued before opening a different row in the same bank. figure10 : active command clk /clk cke /cs notes : 1. ra : row address 2. ba : bank address /ras /cas /we ra a0~a11 once a row is open(with an active command) a read or write command may be issued to that row, subject to the trcd specification. trcd(min) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the active command on which a read or write command can be entered. a subsequent active command to a different row in the same bank can only be issued after the previous active row has been ba ba0, ba1 don ?t care figure11 : trcd, trrd, trc closed(prechar g e). t he minimum time interval between successive active commands to the same bank is defined by trc. a subsequen t active command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. the minimum time interval between successive active commands to different banks is defined by trrd. /clk t0 t1 t2 t3 t4 ta0 ta1 ta2 rd/wt with ap act nop nop nop row act nop cl k command a0 - a1 1 col row row act tch tcl tis tih tck 26 rev. a | april 2010 www.issi.com - dram@issi.com bank a ba0, ba1 bank a trcd don ? t care bank b trrd bank a trc
is43/46lr16800e read the read command is used to initiate a burst read to an active row. the value of ba0 and ba1 selects the bank and address inputs select the starting column location . the starting column location . the value of a10 determines whether or not auto-precharge is use d. if auto-precharge is selected , the row being accessed will be precharged at the end of the read burst; if auto precharge is not selected, the row will remain open for subsequent access. the valid data- out elements will be available cas latency after the read command is issued. the mobile ddr drives the dqs during read operations. the initial l owstateofthedqsisknownasthereadpreambleandthelastdata- out element is coincident with the read posta mble. dqs is edge-aligned with read data. upon completion of a burst, assuming no new read commands have been initiated, the i/o's will go high-z. figure12 : read command clk /clk cke /cs /ras notes : 1. ca : column address 2. ba : bank address 3. a10=high : enable auto precharge a10=low : disable auto precharge /cas /we ca a0~a8 a10 ba ba 0 ba 1 don ? tcare figure13 : read data out timing (bl=4) ba ba 0 , ba 1 don t care /clk clk t0 t1 t2 t3 t1n t2n t3n t4 t4n bank a col n command read nop nop nop nop address dqs cl =2 trpre tac trpst dqs dq cl=3 d out n+1 trpre trpst d out n d out n+2 d out n+3 d ? t tac tdqsck t q h tlz thz tdqsq dq d out n+1 d out n d out n+2 d out n+3 27 rev. a | april 2010 www.issi.com - dram@issi.com notes: 1. bl=4 2. shown with nominal tac, tdqsck and tdqsq d on ? t care q
is43/46lr16800e figure14 : consecutive read bursts (bl=4) t 0 t 1 t 2 t 3 t 4 t 5 bank a col m bank a col n nop read nop nop nop read t 0 t 1 t 2 t 3 address t 4 t 5 /clk clk command d out m dq cl=3 dqs don ? t care d out n+1 d out n d out n+2 d out n+3 d out m+1 figure15 : non consecutive read bursts (bl 4) notes: 1. dout n or m = data-out from column n or m 2. bl=4,8,16 (if 4, the bursts are concatenated; if 8 or 16, the second burst interrupts the first) 3. shown with nominal tac, tdqsck and tdqsq figure15 : non - consecutive read bursts (bl = 4) bank a col m bank a col n nop read nop nop nop read t0 t1 t2 t3 address t4 t5 /clk clk command nop col m col n dq cl=3 dqs don ? t care d out n+1 d out n d out n+2 d out n+3 cl=3 d out m d out m+ 1 notes: 1. dout n or m = data-out from column n or m 2. bl=4,8,16 (if 4, the bursts are concatenated; if 8 or 16, the second burst interrupts the first) 3. shown with nominal tac, tdqsck and tdqsq 28 rev. a | april 2010 www.issi.com - dram@issi.com
is43/46lr16800e figure16 : random read access bank a col m bank a col p bank a col q bank a col n read read read nop nop read t0 t1 t2 t3 address t4 t5 /clk clk command nop d out p dq cl=3 dqs don ? t care d out n+1 d out n d out m d out m+1 d out q d out q+1 d out p+1 truncated reads notes: 1. dout n or m,p,q = data-o ut from column n or m,p,q 2. bl=2,4,8,16 (if 4,8 or 16, the following burst interrupts the previous) 3. reads are to an active row in any bank. 4. shown with nominal tac, tdqsck and tdqsq data from any read burst may be truncated with a burst terminate command, as shown in fi g ure16. the burst terminate latency is equal to the read (cas) latency, i.e., the burst terminate command should be issued x cycles after the read command, where x equals the number of desired data element pairs (pairs are required by the 2n-prefetch architecture). data from any read burst must be completed or truncated befo re a subsequent write command ca n be issued. if truncation is necessary, the burst terminate command must be used. a read burst may be followed by, or truncated with, a precharge command to the same bank provided that auto precharge was not activated. the precharge command should be issued x cycles after the read command, where x equals the number of desired data element pairs (pairs are required by the n- prefetch architecture). this is shown in figure (read to precharge). following the precharge command a subsequent command to the same bank cannot be issued until trp is met figure17 : read burst terminate (bl=4,8 or 16) precharge command , a subsequent command to the same bank cannot be issued until trp is met . nop read bst nop nop t0 t1 t2 t3 t4 /clk clk command bank a col n address dq cl= 3 dqs d out n+1 d out n 29 rev. a | april 2010 www.issi.com - dram@issi.com notes: 1. dout n = data-out from column n 2. cke=high 3. shown with nominal tac, tdqsck and tdqsq don ? t care
is43/46lr16800e figure18 : read to write terminate (bl=4,8 or 16) bank a col m nop bank a col n nop read bst write nop t0 t1 t2 t3 address t4 /clk clk cl = 3 command td q ss t5 notes: 1 dout n = data - out from column n din m = data - in from column m dq dqs don ? t care d out n+1 d out n q (nom ) d in m d in m+1 figure19 : read to precharge (bl 4) 1 . dout n = data out from column n , din m = data in from column m . 2. cke=high 3. shown with nominal tac, tdqsck and tdqsq figure19 : read to precharge (bl = 4) bank a (a, or all ) bank a col n pcg read nop act nop nop t0 t1 t2 t3 address t4 t5 /clk clk command bank a row notes: dq cl = 3 dqs trp don ? t care d out n+1 d out n d out n+2 d out n+3 notes: 1. dout n = data-out from column n. 2. read to precharge equals 2 tck, which allows 2 data pairs of data-out. 3. shown with nominal tac, tdqsck and tdqsq 30 rev. a | april 2010 www.issi.com - dram@issi.com
is43/46lr16800e write the write command is used to initiate a burst write access to an active row. the value of ba0, ba1 selects the bank and address inputs ltth tti l l ti se l ec t th e s t ar ti n g co l umn l oca ti on. the value of a10 determines whether or not auto precharge is used.if autoprecharge is selected , the row being accessed will be precharged at the end of the writ e burst; if auto precharge is not selected, the row will remain open fo r subsequent access. in put data appearing on the data bus, is written to the memory array subjec t to the dm input logic level appearing coincident with the dat a. if a given dm signal is registered low, the corresponding data will be written to the memory; if the dm signal is registered high, the cor responding data-inputs will be ignored, and a write will not be executed to that byte/column location. the memory controller drives the dq sduring write operations. the initial low state of the dqs is known as the write preamble and the low state following the last data-in element is write postamble. upon completion of a burst, assu ming no new commands have been initiated, the i/o's will stay high-z and any additio nal input data will be ignored. data will be ignored. figure20 : write command clk /clk cke /cs notes : 1. ca : column address 2. ba : bank address 3. a10=high : enable auto precharge a10=low : disable auto precharge /ras /cas /we ca a 0 ~a 8 fi g ure21 : write burst ( bl=4 ) 0 8 a10 ba ba0, ba1 don ? t care g() bank a col m bank a col n write nop write /clk clk t0 t1 t2 t3 t1n t2n address command dq tdqss twpst dqs twpres twpre tdh tds d m d in n d in n+1 d in n+2 d in n+3 tdqsh 31 rev. a | april 2010 www.issi.com - dram@issi.com notes: 1. din n = data-in from column n. don ? t care d m
is43/46lr16800e figure22 : consecutive write to write (bl=4) write write nop nop nop nop bank a col n bank a col m t0 t1 t2 t3 address t4 t5 /clk clk td q ss command d in m dqs dq q (nom ) dm d in n d in n+1 d in n+2 d in n+3 d in m+ 1 d in m+2 d in m+ 3 don?t care fi 23 n ctiwittit(bl4) notes: 1. din n = data-in from column n. 2. each write command may be to any banks. fi gure 23 : n on- c onsecu ti ve w r it e t o wr it e (bl = 4) nop write nop nop write nop bank a col n t0 t1 t2 t3 address t4 t5 /clk clk command bank a col m nop d in m dqs dq tdqss (nom ) dm d in n d in n+1 d in n+2 d in n+3 d in m+ 1 d in m+2 d in m+ 3 don ? tcare tdqss (nom ) notes: 1. din n = data-in from column n. 2. each write command may be to any banks. don t care 32 rev. a | april 2010 www.issi.com - dram@issi.com
is43/46lr16800e figure24 : random write to write bank a col q bank a col p write write write write nop bank a col n bank a col m t0 t1 t2 t3 address t4 /clk clk command d in q+ 1 d in m dqs dq tdqss (nom) dm d in n d in n+1 d in p d in p+1 d in m+1 d in q figure25 : write to read (uninterrupting) notes: 1. din n,p,m,q = data-i n from column n,p,m,q. 2. each write command may be to any banks. don?t care figure25 : write to read (uninterrupting) nop write bk nop nop read nop bk t0 t1 t2 t3 t4 t5 /clk clk command nop nop t6 t7 b an k a col m b an k a col n address dqs dq tdqss (nom) d in n d in n+1 d in n+2 d in n+3 cl=3 d out m+ 1 d out m twtr d out m+2 notes: 1. din n = data-in from column n, dout m = data-out from column m. 2. twtr is referenced from the first positive ck edge after the last data-in pair. 3. read and write command can be directed to different banks, in which case twtr is not required and the read command could be applied ealier. dm don?t care 33 rev. a | april 2010 www.issi.com - dram@issi.com
is43/46lr16800e figure26 : write to read (interrupting) write nop t6 t7 nop nop read nop bank a col n t0 t1 t2 t3 address t4 t5 /clk clk command bank a col m nop nop dqs dq tdqss (nom) dm d in n d in n+1 cl=3 d out m+1 d out m d out m+2 d out m+ 3 tw t r figure27 : write to read (odd number of data interrupting) notes: 1. din n = data-in from column n, dout m = data-out from column m. 2. twtr is referenced from the first positive ck edge after the last data-in pair. don ?t care figure27 : write to read (odd number of data interrupting) t6 t7 t0 t1 t2 t3 t4 t5 write nop nop nop read nop bank a a ddress /clk clk command bank a nop nop dqs dq tdqss (nom) dm d in n cl=3 d out m+1 d out m d out m+2 d out m+ 3 tw t r col n a ddress col m notes: 1. din n = data-in from column n, dout m = data-out from column m. 2. twtr is referenced from the first positive ck edge after the last data-in pair. dm don?t care 34 rev. a | april 2010 www.issi.com - dram@issi.com
is43/46lr16800e figure28 : write to precharge (uninterrupting) pcg nop write nop nop nop bank a col n t0 t1 t2 t3 address t4 t5 /clk clk command dqs dq tdqss (nom) dm d in n d in n+1 d in n+2 d in n+3 twr figure29 : write to precharge (interrupting) notes: 1. din n = data-in from column n. 2. twr is referenced from the first positive ck edge after the last data-in pair. 3. read and write command can be directed to different banks, in which case twr is not required and the read command could be applied ealier. don?t care figure29 : write to precharge (interrupting) nop write nop nop pcg nop bank a t0 t1 t2 t3 a dd t4 t5 /clk clk command bank a col n a dd ress dqs dq tdqss (nom) d in n d in n+1 twr notes: 1. din n = data-in from column n. 2. twr is referenced from the first positive ck edge after the last data-in pair. 3. read and write command can be directed to different banks, in which case twr is not required and the read command could be applied ealier. dm don? t care 35 rev. a | april 2010 www.issi.com - dram@issi.com
is43/46lr16800e figure30 : write to precharge (odd number of data interrupting) t 0 t 1 t 2 t 3 t 4 t 5 nop write nop nop pcg nop bank a col n t 0 t 1 t 2 t 3 address t 4 t 5 /clk clk tdqss command twr dqs dq tdqss (nom) dm d in n twr notes: 1. din n = data-in from column n. 2. twr is referenced from the first positive ck edge after the last data-in pair. 3. read and write command can be directed to different banks, in which case twr is not required and the read command could be applied ealier. don? t care 36 rev. a | april 2010 www.issi.com - dram@issi.com
is43/46lr16800e precharge the precharge command is used to deactivate the open row in a particu lar bank or the open row in all banks. the banks will be available for subsequent row access some specified time (trp) after the precharge command issued . for subsequent row access some specified time (trp) after the precharge command issued . input a10 determines whether one or all banks are to be precharged. in the case where only one bank is to be precharged (a10=low), inputs ba0,ba1 select the banks. when all banks are to be precharged (a10=high), inputs ba0,ba1 are treated as a ?don?t care?. once a bank has been precharged, it is in the idle state and must be actived prior to any read or write commands being issued to that bank. figure31 : precharge command clk /clk cke /cs /ras notes : 1. ba : bank address /cas /we ba a10 ba0, ba1 don ?t care mode register the mode register contains the sp ecific mode of operation of the mobile ddr sdram. this register includes the selection of a bur st length (2,4,8,16),acaslatency(2,3),abursttype.themoderegistersetmustbedonebefore any activate command after the power up ( 2, 4, 8, 16), a cas latency(2, 3), a burst type. the mode register set must be done before any activate command after the power up sequence. any contents of the mode register be altered by re-programming th e mode register through the execution of mode register set comm and. 012345 6 78 /clk clk 910 figure32 : mode resister set t ck 2 ck min clk cmd t rp precharge all bank mode resister set command (any) 37 rev. a | april 2010 www.issi.com - dram@issi.com
is43/46lr16800e auto refresh the auto refresh command is used during norm al operation of the mobile ddr. it is non persistent, so must be issued each time a refresh figure33 : auto refresh is required. the refresh addressing is generated by the internal refresh controller. the mobile ddr requires auto refresh comma nds at an average periodic interval of trefi. to allow for improved effi ciency in scheduling and switchin g between tasks, some flexibilit yin the absolute refresh interval is provided. a maximum of eight auto refresh commands can be posted to any given mobile ddr, and the maximum absolute interval between any auto refresh co mmand and the next auto refresh command is 8*trefi. /clk t0 t1 t3 tb0 t2 t4 ta 0 tb 0 ta2 aref nop nop nop aref pcg nop clk cke command tch tcl tis tih tck valid a0~a9, a11 all banks act nop ra nop valid tis tih dqs, dq, dm a10 trp don?t care all banks one bank ba ba 0, ba 1 ra ba trfc trfc self refresh this state retains data in the mobile ddr, even if the rest of the system is powered down (even without external clocking). not e refresh interval timing while in self refresh mode is scheduled internally in the mobile ddr and may vary and may not meet trefi time. "don't care" except cke, which must remain low. an internal refresh cy cle is scheduled on self refres h entry. the procedure for exitin gself refresh mode requires a series of commands. first clock must be stable before cke going high. nop commands should be issued for the duration of the refresh exit time (txsr), because time is required for the completion of any internal refresh in progress. the use of self refresh mode introduces the possibility that an internally timed event can be missed when cke is raised for exit from self re fre sh mode figure34 : self refresh refresh mode introduces the possibility that an internally timed event can be missed when cke is raised for exit from self re fre sh mode . /clk c l k t0 t1 ta0 tb0 ta1 valid nop aref nop c l k cke command tis tih address tis tih tis tis valid 38 rev. a | april 2010 www.issi.com - dram@issi.com dqs, dq, dm trp don?t care txsr self-refresh mode entry self-refresh mode exit
is43/46lr16800e power down power down occurs if cke is set low coincident with device desele ct or nop command and when no ac cesses are in progress. if po wer down occurs when all banks are idle, it is precharge power down. if power down occurs when one or more banks are active, it i sr eferred to figure35 : power down (active or precharge) down occurs when all banks are idle, it is precharge power down. if power down occurs when one or more banks are active, it i s r eferred to as active power down. the device cannot stay in this mode for longer than the refresh requirements of the device, without losin g data. the power down state is exited by setting cke high while issuing a device deselect or nop command. a valid command can be issued af ter txp. / cl k t0 t1 ta0 t2 ta1 tb0 valid nop nop valid / clk cke command tch tcl tis tih tck tis tis tih txp dqs, dq, dm valid address valid tis tih must not exceed refresh device limits don ? t care deep power down the deep power-down (dpd) mode enables very low standby currents. all internal voltage generators inside the mobile ddr are sto pped and all memory data is lost in this mode. all the information in the mode register and the extended mode register is lost. next figure, deep power-down command shows the deep power-down command all banks must be in idle state with no activity on the data bus prior to entering the dpd mode. while in this state, cke must be held in a constant low state. to exit the dpd mode, cke is taken high af ter the clock is stable and nop command must be maintained for at least 200 us. power-down mode entry power-down mode exit figure36 : deep power down /clk clk t0 t1 ta0 tb0 tcke tis t2 ta1 ta2 t=200us valid nop nop dpd nop cke command address valid 39 rev. a | april 2010 www.issi.com - dram@issi.com dqs, dq, dm don?t care deep power -down mode entry deep power-down mode exit
is43/46lr16800e clock stop mode clock stop mode is a feature supported by mobile ddr sdram devi ces. it reduces clock-related po wer consumption during idle perio ds of the device. the device. conditions: the mobile ddr sdram supports clock stop in case: ? the last access command (active, read, write, precharge, au to refresh or mode register set) has executed to completion, including any data-out during read bursts; the number of required clock pulses per access command depends on the device's ac tim ing parameters and the clock frequency; ? the related timing condition (trcd, twr, trp, trfc, tmrd) has been met; ? cke is held high. when all conditions have been met, the device is either in ''i dle'' or ''row active'' state, and clock stop mode may be entered with ck held low and /ck held high. clock stop mode is exited when the clock is restarted. nops command have to be issued for at least one cl ock cycle before the next access command may be applied. additional clock pulses mi g ht be required dependin g on the system characteristics. figure37 illustrates the clock stop mode: ? initially the device is in clock stop mode; ? the clock is restarted with the rising edge of t0 and a nop on the command inputs; ? with t1 a valid access command is latched; this command is followed by nop commands in order to allow for clock stop as soon as this access command has completed; ?t n is the last clock pulse required by the access command latched with t1. ? the timing condition of this access command is met with the completion of t n ; therefore tn is the last clock pulse required by this command and the clock is then stopped command and the clock is then stopped . figure 37 : clock stop mode t0 t1 t2 t n / clk cke / clk clk timing condition high dq,dqs (high ? z) add cmd don ? tcare nop cmd nop nop nop valide exit clock stop mode enter clock stop mode v ail command clock stopped don t care 40 rev. a | april 2010 www.issi.com - dram@issi.com
is43/46lr16800e ordering information ? vdd = 1.8v configuration frequency (mhz) speed (ns) order part no. package 8mx16 166 6 is43lr16800e-6bl 60-ball bga, lead-free commercial range: (0 o c to +70 o c) industrial range: ( - 40 o cto+85 o c) configuration frequency (mhz) speed (ns) order part no. package 8mx16 166 6 is43lr16800e-6bli 60-ball bga, lead-free industrial range: ( 40 c to +85 c) automotive: (-40 o c to +85 o c) note: the -6 speed option supports -75 and -10 timing specifications. configuration frequency (mhz) speed (ns) order part no. package 8mx16 166 6 IS46LR16800E-6BLA1 60-ball bga, lead-free 41 rev. a | april 2010 www.issi.com - dram@issi.com
is43/46lr16800e 42 rev. a | april 2010 www.issi.com - dram@issi.com

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